Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 1 Overview
FEUL620Q504 1–3
•
Successive approximation type A/D converter (SA-ADC)
−
Input
×
12 channels
−
12-bit A/D converter
−
Starting by trigger of Timer/FTM function.
−
Capacitive touch sense function
•
Analog Comparator (CMP)
−
Input
×
2 ch
−
Common mode input voltage: 0.2V to V
DD
- 0.2V
−
Input offset voltage: 30mV(max)
−
Interrupt allow edge selection and sampling selection are selectable
•
Voltage Level Supervisor (VLS)
−
Threshold voltages: selectable from 9 levels
−
interrupt or reset generate are slectable
•
Low Level Detector(LLD)
−
Judgment Voltage: 1.8V
±
0.2V
−
Usable as low level detection reset
•
Reset
−
Reset by the RESET_N pin
−
Reset by power-on detection
−
Reset by overflow of watchdog timer (WDT)
−
Reset by Voltage Leve Supervisor(VLS)
−
Reset by Low Level Detector(LLD)
•
Clock
−
Low-speed clock: (This LSI can not guarantee the operation without low-speed clock)
−
Crystal oscillation (32.768 kHz)
−
External clock input (30kHz to 36kHz)
−
Built-in RC oscillation (32.768kHz)
−
High-speed clock:
−
Crystal/Ceramic oscillation (16 MHz)
−
External clock input (300kHz to 16 MHz)
−
Built-in RC oscillation (16MHz)
•
Power management
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HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating states.
−
HALT-H mode: Instruction execution by CPU is suspended. Stop of high-speed oscillation automatically. All
peripheral circuits can keep in operating states.
−
DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTBC etc.) can
keep in operating states.
−
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits
are stopped.)
−
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8,1/16,1/32 of
the oscillation clock)
−
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.