Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-11
14.2.6 UARTF0 Line Status Register (UAF0LSR)
Address: 0F7C8H
Access: R
Access size: 8/16 bits
Initial value: 0060H
7 6 5 4 3 2 1 0
UAF0LSRL UF0RFE
UF0TEMT UF0THRE
UF0BI UF0FER UF0PER UF0OER UF0DR
R/W R R R R R R R R
Initial value 0 1 1 0 0 0 0 0
15 14 13 12 11 10 9 8
UAF0LSRH – – – – – – – –
R/W R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
UAF0LSR is a special function register (SFR) used to display the status.
UAF0LSR is normally the first register read out by the CPU for determining the interrupt cause or for polling the
status of the serial communication channel.
UF0OER, UF0PER, UF0FER, and UF0BI are error conditions, which generate a received data error interrupt (a
LVL=1 interrupt in the IIR) if any of the states is detected. This interrupt is enabled by setting UF0ELSI of
UARTF0IER to 1.
Description of Bits
•
UF0DR (bit 0)
UF0DR is set to 1 when the input character has been received and transmitted to RBR. This bit is cleared
when the RBR data is read.
UF0DR Description
0 No valid data in RBR (initial value)
1 There is valid data in RBR
•
UF0OER (bit 1)
UF0ER indicates that an overrun error occurred. The overrun error indicates that the CPU did not read
the data in RBR before the next character was sent to RBR to overwrite the previous character. In FIFO
mode, an overrun error occurs after the FIFO has become full when the next character is completely
received. Reading UAF0LSR after an overrun error will clear the overrun error. The character during
reception is overwritten instead of being transferred to FIFO. This bit is cleared when UAF0LSR is read.
UF0OER Description
0 No overrun error (initial value)
1 Overrun error occurred