ML620Q503/Q504 User's Manual
Chapter 20 Port 3
FEUL620Q504 20–5
20.2.2 Port 3 Data Register (P3D)
Address: 0F228H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
P3D
P37D
P36D
P35D
P34D
P33D
P32D
P31D
P30D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of
the Port 3. In output mode, the value of this register is output to the Port 3 pin. The value written to P3D is
readable. In input mode, the input level of the Port 3 pin is read when P3D is read.
Output mode or input mode is selected by using the port mode register (P3DIR) described later.
Description of Bits
•
P37-30D
(bits 7 to 0)
The P37-30D bits are used to set the output value of the Port 3 pin in output mode and to read the pin
level of the Port 3 pin in input mode.
P30D
Description
0
Output or input level of the P30 pin: ”L”
1
Output or input level of the P30 pin: ”H”
P31D
Description
0
Output or input level of the P31 pin: ”L”
1
Output or input level of the P31 pin: ”H”
P32D
Description
0
Output or input level of the P32 pin: ”L”
1
Output or input level of the P32 pin: ”H”
P33D
Description
0
Output or input level of the P33 pin: ”L”
1
Output or input level of the P33 pin: ”H”
P34D
Description
0
Output or input level of the P34 pin: ”L”
1
Output or input level of the P34 pin: ”H”
P35D
Description
0
Output or input level of the P35 pin: ”L”
1
Output or input level of the P35 pin: ”H”
P36D
Description
0
Output or input level of the P36 pin: ”L”
1
Output or input level of the P36 pin: ”H”
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...