Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 2 CPU and Memory Space
FEUL620Q504 2–7
2.7.2.2 Operation Mode Register (CR8)
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
CR8 CLEN – – SIGN – CLMOD2 CLMOD1 CLMOD0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The operation mode register sets the operation mode.
The bit symbol cannot be used in the program.
Description of Bits
•
CLMOD2-0 (bits 2 to 0)
The CLMOD2-0 bits are used to select the operation mode. The mode can be selected from
multiplication, division, multiply-accumulate (non-saturating) and multiply-accumulate (saturating).
CLMOD2 CLMOD1 CLMOD0 Description
0 0 0 Multiplication
(initial value)
16bit * 16bit
0 0 1 Division 32bit / 16bit
0 1 0 Multiply-accumulate
(non-saturating) 16bit * 16bit + 32bit
0 1 1 Multiply-accumulate
(saturating) 16bit * 16bit + 32bit
1 0 0 Reserved
1 0 1 Division 32bit / 32bit
1 1 * Reserved
•
SIGN (bit 4)
SIGN is a bit to set the sign operation.
SIGN Description
0 Unsigned operation (initial value)
1 Signed operation
•
CLEN (bit 7)
CLEN is a bit to set whether or not to enable the operation.
CLEN Description
0 Operation prohibited (initial value)
1 Operation enabled
* Operation does not start unless CLEN is set to "1".
Also, if CLEN is cleared to "0" during an operation, the next operation does not start after that
operation ends.