ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504
13–3
13.2.2
UART0 Receive Buffer (UA0BUF)
Address: 0F710H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
UA0BUF
U0B7
U0B6
U0B5
U0B4
U0B3
U0B2
U0B1
U0B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UA0BUF is a special function register (SFR) used to store the received data.
Since data received at termination of reception is stored in UA0BUF, read the contents of UA0BUF using the
UART0 interrupt at termination of reception. At continuous reception, UA0BUF is updated whenever reception
terminates. Any write to UA0BUF is disabled.
When the 5- to 7-bit data length is selected, unnecessary bits become "0".
13.2.3
UART0 Transmit Buffer (UA1BUF)
Address: 0F718H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
UA1BUF
U1B7
U1B6
U1B5
U1B4
U1B3
U1B2
U1B1
U1B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UA1BUF is a special function register (SFR) used to store the transmitted data.
Write data to be transmitted in the UA1BUF. To transmit data consecutively, confirm the U1FUL flag of the
transmit status register (UA1STAT) becomes "0", then write the next transmitted data to UA1BUF. Any value
written to UA1BUF can be read. When the 5- to 7-bit data length is selected, unnecessary bits become invalid in
the transmit mode.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...