ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–30
The period is calculated as follows:
T
priod
=
FTnP + 1
(FTnP : 0001H to FFFFH)
FTnCK [Hz]
6: Output setting (FTOSL*, Each Port Setting)
Set which output to which port, and reverse.
7: Control start/stop (FTnCON0)
Allow the software start or event trigger reception. Also, set the emergency stop enable.
The counter operates at a falling edge of FTnCK. The software start/stop are synchronized by FTnCK.
FTnSTAT is set to H after FTnCK1 cycle at start, and the counter starts operating after two cycles. At stop,
the counter is stopped in FTnCK1 cycle, and FTnSTAT is set to L. The counter value is kept at this time. If
started again, it restarts after one cycle. To clear the counter, use write access to FTnC.
8: Processing during operation (FTnCON0/1, FTnINTS/C)
The state during operation can be seen in FTnCON1 or FTnINTS. To change the waveform of PWM, etc., set
the period/event and set FTnUD of FTnCON1. Then, it is updated in the next period. Also, setting FTnSDN
of FTnCON0 forces the output to be masked to L.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...