Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-12
4.3.1.2 DEEP-HALT Mode
During the DEEP-HALT mode, the CPU interrupts execution of instructions, and the entire circuit stops
operating except for some peripheral blocks such as watchdog timer and LTBC.
When the DHLT bit of the standby control register (SBYCON) is set to “1”, the mode changes to the
DEEP-HALT mode.
When a WDT interrupt request, or an enabled interrupt request (the interrupt enable flag is “1”) is issued, the
DHLT bit is set to “0” on the falling edge of the next system clock (SYSCLK), the DEEP-HALT mode is
released, and the mode returns to the program run mode.
When the DHLT bit is set to “1” during operation with the high-speed clock, the clock switches to the low-speed
clock and the mode changes to the DEEP-HALT mode. If a WDT interrupt request, or an enabled interrupt
request (the interrupt enable flag is “1”) is issued in this state, DHLT is set to “0”, the mode returns to the
program run mode, and the clock is switched to the high-speed clock again.
Restart of a high-speed clock is not related to the clock mode. When low-speed clock counts 29, after the
interrupt request is generated, high-speed built-in RC oscillation starts oscillation. And the counts 512, as
OSCLK clock supply. When a system clock is a high-speed clock, it returns to program operational mode
simultaneously.
In the case of high-speed crystal oscillation mode, oscillation is started after high-speed oscillation start time
(T
XTH
) from LSCLK supply. And, OSCLK changes from RC oscillation into crystal oscillation by the
automatically in case of the crystal oscillation counts 4096.
In the case of high-speed external clock mode, OSCLK changes from RC oscillation into external clock by the
automatically in case of the external clock counts 128 from LSCLK supply.
Figure 4-3 shows the operation waveforms in the DEEP-HALT mode.
SYSCLK
LSCLK
Program run mode DEEP-HALT mode
Interrupt request
Program run mode
SBYCON.DHLT
HSCLK
Figure 4-3 Operation Waveforms in DEEP-HALT Mode
[Note]
•When High speed crystal/ceramic oscillator is used and the mode switch to DEEP – HALT mode, Frequency
Status Register (FSTAT) HOSCS bit must be “0”.
•When Low speed crystal oscillator or external clock is used and the mode switch to DEEP – HALT mode,
Frequency Status Register (FSTAT) LOSCS bit must be “0”.
•After release of the DEEP-HALT mode, interrupts other than WDT interrupt start being processed if they are
enabled (“1”) by the MIE bit of PSW.
For details of PSW, refer to “nX-U16/100 Core Instruction Manual”
•Since up to two instructions are executed during the period between DEEP-HALT mode release and a
transition to interrupt processing, place two NOP instructions next to the instruction that sets the DHLT bit to
“1”.