ML620Q503/Q504 User’s Manual
Chapter 1 Overview
FEUL620Q504 1–10
1.3.3 Description of Pins
In the table below indicates the functional pin description.
The pin name represents the function pin name of the primary function of each terminal, The pin mode represents the set
of mode register of Port Control.
(1
st
:primary function, 2
nd
:secondary function, 3
rd
: tertiary function, 4
th
: quartic function)
Pin name
I/O
Description
LSI pin name
Pin mode
Logic
System
RESET_N
I
Reset input pin. When this pin is set to a “L” level,
system reset mode is set and the internal section is
initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up
resistor is internally connected.
RESET_N
–
L
XT0
I
Crystal connection pin for low-speed clock.
Capacitors C
DL
and C
GL
are connected across this pin
and V
SS
as required.
PXT0
1st
–
XT1
O
PXT1
1st
–
LSCLKI
I
External clock input for Low-speed clock.
PXT1
1st
–
OSC0
I
Crystal/ceramic connection pin for high-speed clock
(16 MHz max.). Capacitors C
DH
and C
GH
are
connected across this pin and V
ss
.
P10
1st
–
OSC1
O
P11
1st
–
CLKIN
I
External clock input for High-speed clock.
P11
1st
–
LSCLKO
O Low-speed clock output pin.
P46,P56
2nd
–
OUTCLK
O High-speed clock output pin.
P47,P57
2nd
–
General-purpose input/output port
PXT0-PXT1
I
General-purpose input port(without pull-up/pull-down
resister).
PXT0-PXT1
1st
–
P00-P05
I/O General-purpose input/output port.
P00-P05
1st
–
P10-P11
I/O General-purpose input/output port.
P10-P11
1st
–
P20-P23
I/O General-purpose input/output port.
P20-P23
1st
–
P30-P37
I/O General-purpose input/output port.
P30-P37
1st
–
P40-P47
I/O General-purpose input/output port.
P40-P47
1st
–
P50-P57
I/O General-purpose input/output port.
P50-P57
1st
–
External interrupt
EXII0-EXII1
EXI00-05
EXI20-23
EXI30-37
EXI40-47
EXI50-57
I
External maskable interrupt input pins. It is possible, for
each bit, to specify
whether the interrupt is enabled and select the interrupt
edge by software.
PXT0-PXT1
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
1st
H/L
LED
LED
O N-channel open drain output pins to drive LED.
P40,P41,P52,P53
1st
–
Melody/Buzzer
MD0
O Melody/buzzer signal output pin.
P33,P43,P53
2nd
H
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...