Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-17
14.3.2 Data Reception
Figure 14-4 shows the reception timing. Figure 14-5 shows the timing when the first byte in the receive FIFO is
read, and Figure 14-6 the reception timing when the remaining bytes in the receive FIFO are read.
The sampling clock is obtained by dividing the baud rate clock by 8.
First, when the start bit is detected from RXDF0, subsequent data is obtained and transferred to the receive shift
register. The data in the receive shift register is transferred to RBR through the receive FIFO.
When the data reaches RBR, UF0DR of UAF0LSR is set to "1" to indicate there is valid data in RBR. This bit is
cleared by reading the data in RBR.
8 Clock
Baud rate Clock
Sample CLK
Figure 14-3 Relation between Baud Rate Clock and Sample CLK
RXDF0 Start Data bit (5
～
8) Parity Stop
Sample CLK
UAF0INT
(Received Data Available)
tSINT tRINT
UAF0INT
(Received Line Status)
tRINT
RD
LSR read RBR read
tSINT: MAX 1000ns
tRINT: MAX 1 Baud rate Clock
Figure 14-4 Reception Timing