ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–44
9.3.7.3 Emergency Stop Operation
When FTnEMGEN is set to "1", the emergency stop function is enabled. Set this bit after the trigger source is
selected in FTnEST.
If an emergency stop trigger input (rising edge) is detected, the counter stops, the output is set to L, and an
emergency stop interrupt occurs.
To restart the counter, clear the emergency stop interrupt status (write "1" to FTnICES) and "1" is set to run bit.
Figure 9-9 shows the operation timing at emergency stop.
After the emergency stop, the RUN bit is cleared to 0, the counter stops after one timer clock, and the STAT bit
is cleared to 0. When the STAT bit is 1, setting the RUN to 1 is not accepted. Confirm that the STAT has
changed to 0 after clearing the interrupt status before running the next RUN.
Figure 9-9 Operation Timing Diagram at Emergency Stop
Emergency
stop trigger
FTnRUN
FTnISES
FTMnP/N
FTnC
0000
Count up
0000
Count up
Counting stopped
Count up
0000
Count up
(2)
(3)
(4)
(5)
(1) The counter operation starts at an event trigger (falling edge).
(2) The counter stops at an emergency stop trigger (rising edge). An emergency stop interrupt occurs.
(3) The event trigger is disabled due to the emergency stop in progress.
(4) Clear the emergency stop interrupt to enable the operation.
(5) The counter operation restarts at an event trigger (falling edge).
(In this example, the pulse output restarts after one cycle because the counter is not cleared)
(1)
Event trigger
for start/stop
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...