Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-21
14.3.5 FIFO Polled Mode
If FIFO is enabled and UF0ELSI, UF0ETBEI, and UF0ERBFI of UAF0IER are "0", the UART operates in the
FIFO polled mode. Since the receiver section and transmitter section can be controlled separately, either one (or
both) can be set to FIFO polled mode. In FIFO polled mode, the states of the receiver and transmitter sections
must be checked by reading out the UAnLSR (since no interrupt is generated).
•
A state in which at least one character is present in the receive FIFO can be confirmed by the value "1"
set to UF0DR.
•
When UF0PER is cleared to "0", an interrupt will not be generated even if an error is detected while
receiving a character. The error state will not be indicated on the UAF0IIR value. Therefore, the error
type must be checked with the UF0BI, UF0FER, UF0PER, and UF0OER values.
•
It can be known that the transmit FIFO is empty by the fact that UF0THRE has been set to "1".
•
A state in which the transmit FIFO and transmit shift register are both empty can be confirmed by the
value "1" set to UF0TEMT.
•
A state in which the character associated with an error at the time of reception is present in the receive
FIFO can be confirmed by the value "1" set to UF0RFE.
In FIFO polled mode, FIFO will operate; however, trigger level and timeout detection will not be performed
(since they are only notified by interrupts).