Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–9
26.3.4 Single monitor mode
This mode activate comparator as specified and generate interrupt after measurment, and deactivate comparator
automatically by hardware.
Setting instruction:
(1)Set operation clock, filtering, and single monitor mode by CMPnMOD register.
Interrupt stting is invalid. Only complete interrupt is generated. Also complete interrupt is generated in case
of suspend of operation by software.
(2) Set CMPnEN
(3) After Tend progress, comparator is automatically off and generate complete interrupt. Read
CMPnD(Compare result) from software. CMPnD (Compare result) is kept until “1” is set to CMPnEN.
It is prohibited switch to STOP mode during operation. CMPnEN need to be “0” when switch to STOP mode.
The timing chart is as follows
Figure 26-4 Timing in the single-monitor mode
Time before CMPnD setting becoming valid is depending on operation/sampling clock setting.
CMPn
CK
CMPn
SM1
CMPn
SM0
Operation
clock
Sampling T
end
(Time before turning
off the comparator)
0 0 0
Low speed
LSCLK=32.768kHz
No filtering
3φ
91.6 us
0 0 1 T16KHZ(LTBC output:
1/2 of LSCLK)
4φ
244.2 us
1 0 0
High speed
OSCLK=16MHz
No filtering
4φ
16.0 us
1 1 0 1/64 of OSCLK
5φ
20.0 us
1 1 1 1/128 of OSCLK
4φ
32.0 us
System clock
CMPnCLK
CMPnEN
CMPnOUT
CMPnEN
CMPnD
CMPnRF
CMPnIN
T
with sampling
CMPnEN
CMPnD
CMPnRF
CMPnINT
Tend
Tend
Sampling clock
without sampling