Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504 13–18
13.3.5.1 Detection of Start Bit
The start bit is sampled with the baud rate generator clock (OSCLK). Therefore, the start bit detection may be
delayed for one cycle of the baud rate generator clock at the maximum.
Figure 13-7 shows the start bit detection timing.
Figure 13-7 Start Bit Detection Timing (Positive Logic)
13.3.5.2 Sampling Timing
When the start bit is detected, the received data that was input to the RXD is sampled almost at the center of the
baud rate, then loaded to the shift register.
The loading sampling timing of this shift register can be adjusted for one clock of the baud rate generator clock,
using the U0RSS bit of the UART0 mode register (UA0MOD).
Figure 13-8 shows the relationship between the U0RSS bit and the sampling timing.
(1) When the baud rate generator count value is "7" (odd)
(2) When the baud rate generator count value is "8" (even)
Figure 13-8 Relationship between U0RSS Bit and Sampling Timing
Baud rate generator clock
RXD0
0 3 2 7 0 3 2 7
Sampling timing
U0RSS=1 U0RSS=0
Count value = 8
Sampling by baud rate
generator clock
RXD0
Maximum one-cycle delay
Start bit
Baud rate generator clock
RXD0
0 3 2 6 0 3 2 6
Sampling timing
U0RSS=1 U0RSS=0
Count value = 7