Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-4
4.2.3 Standby Control Register (SBYCON)
Address: 0F009H
Access: W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
SBYCON – – – – HLTH DHLT STP HLT
R/W W W W W W W W W
Initial value 0 0 0 0 0 0 0 0
SBYCON is a special function register (SFR) to control the operation mode of MCU.
Description of Bits
•
HLT (bit 0)
The HLT bit is used for setting the HALT mode. When the HLT bit is set to “1”, the mode is changed to
the HALT mode. Writing “0” to the HLT bit does not change the mode to the HALT mode.
•
STP (bit 1)
The STP bit is used for setting the STOP mode. When the STP bit is set to “1”, the mode is changed to
the STOP mode. Writing “0” to the STP bit does not change the mode to the STOP mode.
Writing to the STP bit should be performed when the stop code acceptor is enabled by using STPACP.
If writing to the STP bit is performed when the stop code acceptor is disabled, the writing becomes
invalid.
•
DHLT (bit 2)
The DHLT bit is used for setting the DEEP-HALT mode. When the DHLT bit is set to “1”, the mode is
changed to the DEEP-HALT mode. Writing “0” to the DHLT bit does not change the mode to the
DEEP-HALT mode.
•
HLTH (bit 3)
The HLTH bit is used for setting the HALT-H mode. When the HLTH bit is set to “1”, the high-speed
clock is stopped by the hardware and the mode is changed to the HALT-H mode. Writing “0” to the
HLTH bit does not change the mode to the HALT-H mode.
Plural these bits cannot be set to “1” at the same time.
[Note]
• When High speed oscillator is used and the mode switch to STOP, DEEP-HALT, or HALT-H mode ,
Frequency Status Register (FSTAT) HOSCS bit must be “0”.
• When Low speed oscillator is used and the mode switch to DEEP-HALT mode, Frequency Status Register
(FSTAT) LOSCS bit must be “0”.
•The mode is not changed to the STOP mode, HALT mode, or DEEP-HALT mode on the condition that any
interrupt enable flag and the corresponding interrupt request flag are both ”1” (for example, an interrupt
request occurs when the MIE flag is ”0”).
•When a maskable interrupt source (interrupt with enable bit) occurs while the MIE flag of the program status
word (PSW) in the nX-U16/100 core is “0”, the STOP mode, HALT mode, and DEEP-HALT mode are
simply released and interrupt processing is not performed. For details of PSW, see “nX-U16/100 Core
Instruction Manual”.