Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 28 Voltage Level Supervisor
FEUL620Q504 28-11
Figure 28-5 shows an example of the operation timing diagram when detecting with sampling and setting the
VLS interrupt issue.
①
Set ENVLS to “1” from the CPU to turn on the VLS.
②
The VLS analog output is stabilized.
③
V
DD
becomes lower than the specified threshold voltage (V
VLS
).
④
The ready flag (VLSRF) is set to ”1” after T16KHZ2
φ
. At the same time, the voltage level detection
flag (VLSF) is set to “1” to issue a VLS interrupt because the VLS analog voltage is lower than the
threshold voltage (V
VLS
).
⑤
V
DD
returns to higher than the threshold voltage of rise (V
VLS
+H
VLS
).
⑥
Because it is judged that a VLS analog voltage sampled at T16KHZ is higher than the threshold
voltage (V
VLS
+H
VLS
),
the voltage level detection flag (VLSF) is set to “0”.
⑦
Set ENVLS to “0” from the CPU to turn off the VLS.
Figure 28-5 Operation Timing Diagram When Detecting with Sampling
and Setting VLS interrupt issue
Sampling Clock
(T16KHZ)
①
↓
Stabilization
time
ENVLS
Threshold voltage
V
VLS
VLS analog output
V
SS
V
DD
Ready flag: VLSRF
↓
↓
↓
↓
Detection flag: VLSF
VLS interrupt
↓
↓
V
VLS
+H
VLS
(rise)
(fall)
② ③ ④
⑤ ⑥
⑦