Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–13
9.2.8 FTMn Control Register 1 (FTnCON1 : n=0,1,2,3)
Address: 0F40BH(FT0CON1), 0F42BH(FT1CON1), 0F44BH(FT2CON1), 0F46BH(FT3CON1)
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
FTnCON1 FTnSTAT FTnFLGC FTnFLGB FTnFLGA – – – FTnUD
R/W R R R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
FTnCON1 is a special function register (SFR) used to set the function of FTMn.
Description of Bits
•
FTnUD (bit 0)
This bit is used to update FTnP, FTnEA, FtnEB and FTnDT of FTMn during operation. To update FTnP,
FTnEA, FtnEB and FTnDT, write "1" to this bit after setting these registers. Writing "1" transfers the
setting values to the internal buffer of FTnP, FTnEA, FtnEB and FTnDT at the same time. When the
transfer completes, this bit is cleared automatically.
FTnMD FTnUD Description
TIMER
CAPTURE
PWM1/2
0 Update completed (initial value)
1 Requesting update
[Note]
To write "1" to this bit (to update register value), do so after reading this bit and confirm that the
value is "0" (update is completed).
•
FTnFLGA (bit 4)
Indicates the state of event timing A of FTMn.
FTnMD FTnFLGA Description
TIMER
PWM1/2
0 Counter value < Value of event register A (initial value)
1 Counter value
≥
Value of event register A
CAPTURE
0 Capture data not available
1 Capture data available. When FTnEA is read, it is cleared
•
FTnFLGB (bit 5)
Indicates the state of event timing B of FTMn.
FTnMD FTnFLGB Description
TIMER
PWM1/2
0 Counter value < Value of event register B (initial value)
1 Counter value
≥
Value of event register B
CAPTURE
0 Capture data not available
1 Capture data available. When FTnEB is read, it is cleared