ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–47
9.3.10 Interrupt Source
This section describes the interrupt source and how to clear it.
When a target interrupt enable (FTnIE*) is set to "1", the interrupt status is enabled, and the interrupt controller
is notified of the source.
Note that the emergency stop interrupt enable does not exist. When the emergency stop is enabled, its interrupt is
also enabled.
If the interrupt status is set to "1" for a source, clear it by an appropriate processing.
When the interrupt vector is used, write "1" to FTnIR at the end of the interrupt processing (when exiting the
interrupt vector).
Name
Mode
Status
How to clear
Period coincident
interrupt
ALL
FTnISP
Write "1" to FTnICP
Event A coincident
interrupt
TIMER/PWM1/PWM2
FTnISA
Write "1" to FTnICA
Capture A interrupt CAPTURE
FTnISA
Write "1" to FTnICA or read FTnEA
Event B coincident
interrupt
TIMER/PWM1
FTnISB
Write "1" to FTnICB
Capture B interrupt CAPTURE
FTnISB
Write "1" to FTnICB or read FTnEB
Trigger stop
interrupt
ALL
FTnISTS
Write "1" to FTnICTS
Trigger start
interrupt
ALL
FTnISTR
Write "1" to FTnICTR
Emergency stop
interrupt
ALL
FTnISES
Write "1" to FTnICES
The period coincident interrupt/event A coincident interrupt/event B coincident interrupt can be selected as
the interrupt trigger output.
Figure 9-11 interrupt controlling
Interrupt notification
Interrupt enable (FTnIE*)
Interrupt source
Interrupt status
(FTnIS*)
REG
Interrupt status clear (FTnIC*)
Interrupt trigger output enable (FTnIO*)
To trigger input of another
FTM/SA-ADC
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...