Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–19
12.3 Description of Operation
12.3.1 Master Mode and Slave Mode
Master mode and Slave mode are provided as the transmit/receive mode. This is selected by the SF0MST bit of
the SIOF0 control register.
SF0BR (baud rate), SF0LEAD (SSF0-SCKF0 delay interval), and SF0LAG (SCKF0-SSF0 delay interval) of the
SIOF0 baud rate register and SF0DTL (minimum data transfer interval) of the SIOF0 transfer interval control
register determine SCKF0 and SSF0 operations and are only valid during the master operation.
Each of SF0CPOL, SF0CPHA, SF0LSB, and SF0SIZ needs to have the same value for master and slave.
12.3.2 Control of Polarity and Phase of Serial Clock
SF0CPOL of the SIOF0 control register controls the clock polarity. SF0CPHA controls the clock phase and
determines the shift timing of transmit data and the sampling timing of received data. The master and slave which
communicate with each other must have the same setting values for SF0CPOL and SF0CPHA.
12.3.3 Data Transfer Timing When SF0CPHA Is "0"
Figure 12-2 shows the data transfer timing when SF0CPHA is "0". For the SCKF0, two cases are shown
(SF0CPOL is "0" and "1"). SSF0 is the slave selection input in Slave mode.
In Master mode, the transfer is started when data is written to the SF0DWR register. In Slave mode, the transfer
is started at the SSF0 falling edge. The received data is sampled at the rising-edge of SCKF0 in SF0CPOL is “0”
and the falling-edge of SCKF0 in SF0CPOL is “1”. The transmitted data is shifted at the falling-edge of SCKF0
in SF0CPOL is “0” and the rising-edge of SCKF0 in SF0CPOL is “1”.
CPHA=0
SCK
(CPOL=0
)
SSN
MOSI
(MOZ=0)
LSB MSB
MSB
MISO
(SOZ=0)
SCK Cycle
1 2 3 4 5 6 7 8
SCK
(CPOL=1
)
LSB
MOZ=SOZ=SSZ=SIZE=LSBF=LEAD=LAG=0
の例
です。
Figure 12-2 Clock Waveform When SF0CPHA = 0
SINF0
SSF0
SCKF0
(SF0CPOL=0)
SCKF0
(SF0CPOL=1)
SOUTF0
SF0CPHA=0
Example for
SF0MOZ=SF0SOZ=SF0SSZ=SF0SIZ=SF0LSB=SF0LEAD=SF0LAG=0.