Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–5
•
CMPnMD1-0 (bit 5 to 4)
Set function mode.
CMPnMD1 CMPnMD0 Description
0 0
Single mode
After CMPnEN is set and complete the compare, if the interrupt condition
is match, generate interrupt and stop automatically.
0 1
Single monitor mode
After CMPnEN is set and complete the compare, generate interrupt and
stop automatically.
1 *
Supervisor mode(initial value)
Compare is started by setting CMPnEN
•
CMPnCK, CMPnSM1-0 (bit 12, 9 to 8)
Set comparator control clock and sampling interval timing for filtering.
Sampling is always disabled regardless of sampling setting during the STOP mode.
CMPnCK CMPnSM1 CMPnSM0
Description
Operation clock Sampling clock and cycle time
0
* 0
Low speed
LSCLK=32.768kHz
No filtering
* 1
T16KHz(LTBC output: 1/2 of
LSCLK)
61us
1
0 *
High speed
OSCLK=16MHz
No filtering -
1 0 1/64 of OSCLK 4us
1
1
1/128 of OSCLK 8us
[Note]
Keep OSCLK working at HALT mode when OSCLK is selected as control clock.
Depending on the operation mode, pay attention in the timing to set STOP mode.
Refer to the 26.3.1.1-3 for STOP mode switching timing of each operation mode.