ML620Q503/Q504 User’s Manual
Chapter 19 Port 2
FEUL620Q504 19–1
19 Port 2
19.1 Overview
This LSI includes Port 2 (P20 to P23) which is an 4-bit input/output port.
This port can have external interrupts, SA-ADC, RC-ADC, SSIOF, UARTF and FTIMER output functions as secondary,
tertiary and quartic functions.
See the following chapters for reference:
FTM:
Chapter 9 “Function Timer”
SSIOF: Chapter 12 “SSIO with FIFO”
UARTF: Chapter 14 “UART with FIFO”
RC-ADC:
Chapter 24 “RC Oscillation type A/D converter”
SA-ADC:
Chapter 25 “Successive approximate type A/D converter”
19.1.1 Features
•
Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS
output for each bit in output mode.
•
Allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor for each bit
in input mode.
•
External interrupt inputs(EXI20,EXI21,EXI22,EXI23), the SA-ADC inputs (AIN4, AIN5, AIN6, AIN7), RC-ADC
(channel 1) oscillation pins (IN1, CS1, RS1, RT1), SSIO with FIFO pins (SINF0, SCKF0, SOUTF0, SSF0), UART
with FIFO pins (RXDF0, TXDF0), TIMER output pin (TMOUT2, TMOUT3) .
19.1.2 Configuration
Figure 19-1 shows the configuration of Port 2.
P2D
:
Port 2 data register
P2DIR
:
Port 2 direction register
P2CON
:
Port 2 control register
P2MOD
:
Port 2 mode register
Figure 19-1 Configuration of Port 2
Data bus
Outputs for SSIOF
(SCKF0,SOUTF0,SSF0)
Output for UARTF (TXDF0)
Outputs for RC-ADC
(CS1, RS1, RT1)
Output for TIMER
(TMOUT2,TMOUT3)
P20
to P23
P2DIR
P2MOD
P2CON
V
DD
V
DD
V
SS
V
SS
4
8
Port2
Output
Controller
P2D
V
DD
V
SS
Pull-up
Pull-down
Controller
Inputs for SSIOF (SINF0)
Input for UARTF (RXDF0)
Input for RC-ADC (IN0)
External Interrupt (EXI20 to EXI23)
3
4
Inputs for SA-ADC
(AIN4, AIN5, AIN6, AIN7)
4
1
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...