Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–24
12.3.8 Transmit Operation (Master Mode)

Write the necessary values to SF0CTRL, SF0INTC, SF0BRR, and SF0TRAC, set the SF0MST bit to
Master mode, and set the SF0SPE bit to enable the SSIOF transfer.

When the transmitted data is written to SF0DWR, the transmit FIFO Empty flag changes to 0 (SF0TFE = 0).
SSIOF starts the automatic transmission and outputs the transmitted data from LSB or MSB on the SOUTF0
pin according to the SF0LSB setting.

The sync clock, which was set by the SF0CPOL, SF0CPHA, and SF0BRR registers, is output from the
SCKF0 pin.

Transmitted data can be written to SF0DWR successively. However, if further writing is performed when
the transmit FIFO is in Full status (SF0TFF = 1), a write overflow occurs. (SF0WOF = 1, No interrupt is
generated.)

The SF0SPIF bit is set each time the transfer of 1 byte is completed. (SF0SPIF=1)

A transmission interrupt occurs if the remaining data in the transmit FIFO matches the byte count selected
with SF0TFIC. (SF0TFI=1)

If the transmit FIFO becomes empty and the transfer of the last byte is completed, a transfer completion
interrupt is generated. (SF0FI=1)
Figure 12-8 Master Mode (Transmit Operation)
SSF0
SCKF0
SOUTF0
SFnSPE
write from
U16IF
read from
U16IF
SF0TFE
SF0TFF
SFnWOF
SF0TFD
SF0TFIC
SSIOF
interrupt
signal
0 2
0 1 1 2
SF0CTRL
data1 data5 data6
SF0SRC
status
3 2 0 3 4 1
status
TFI
Transmission
interrupt
Transfer data 1 Transfer data 3
Transfer data 5
2
4
SF0SRC
FI
transfer end
interrupt