ML620Q503/Q504 User's Manual
Chapter 27
Flash Memory Control
FEUL620Q504 27-
11
27.3.2 Data Flash Rewriting
The LSI is equipped with a data flash of 2 KB (2 sectors: 1 KB/sector). The rewrite count is 10,000.
Figure 27-1 shows the sequence of 1-word write/sector erase/block erase.
Writing is performed sequentially from the first sector. When writing to the second sector is saturated, the first sector is
erased, and the next data is written to it. Thus, up to 1024 * 10,000 times of rewrite is realized when data is written by
one word.
As the initial value after an erase is "FFFFH", the position matching the initial value is searched for as the write position.
Figure 27-1 Data Flash Rewrite Sequence
27.3.3 Program Memory Rewrite (ISP Function)
The program can be rewritten by software by using the ISP function. There are the following two ways to execute the
ISP program:
1) Execute the program by remapping the boot area of the ISP program by software
2) Execute the program by remapping the ISP boot area by hardware at LSI startup
These methods boot the ISP program and rewrite the program memory in the same sequence as the data flash rewrite.
These remap methods is as follows.
Set "1” to FSELF
Set "FA” and "F5” in this order to FLASHACP
Set address to FLASHSEG and FLASHA
Set data to FLASHD
Read/compare from CPU
Any other address
processing?
yes
no
Set "1” to FSERS
Set "1” to FERS
Set "0” to FSELF
(For 1-word write)
(For sector erase)
(For block erase)
(*)
*: The CPU stops during the write/erase processing. Perform the NOP processing twice after this processing.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...