Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 24 RC Oscillation Type A/D Converter
FEUL620Q504 24-19
Figure 24-14 shows, as an example of method, a timing diagram of one cycle of conversion from analog value
RT0 to a digital value, that is, A/D conversion.
Basically, one A/D conversion cycle must consist of two steps, as shown in Figure 24-14. The reason for
requiring two steps is that the reference resistor and the thermistor must first be oscillated separately and then the
ratio between the oscillation frequencies of them is used, as described above.
In the example below, operation for these two steps is performed using the following combination:
•
First step = RC oscillation with RS0 in Counter A reference mode
•
Second step = RC oscillation with RT0 in Counter B reference mode
Besides this, there would be several possible A/D conversion methods.
In the above method, the operation time (gate time) for the second step fluctuates depending on the value of
thermistor RT0. To avoid the fluctuation of the operation time, using a method that uses the following
combination is recommended:
•
First step = RC oscillation with RS0 in Counter B reference mode
•
Second step = RC oscillation with RT0 in Counter A reference mode
A/D conversion procedure is explained below by taking Figure 24-14 as an example.
b
32.768kHz

reference clock
BSCLK
01H
RADMOD
(bit 4
～
0)

01H (ERAD=1)
RADCON
(bit0)
n
c
00H

r
00H
f
12H
CR oscillation
status
（
CROSC0
）
stop stop oscillating RS0 stop oscillating RT0
（
Counter A reference mode
） （
Counter B reference mode
）
0.366 sec
nA0
･
t
BSCLK
=nB0
･
t
RCCLK
(RS0) nB0
･
t
RCCLK
(RT0)=nA1
･
t
BSCLK
(Up count by BSCLK) Counter A
000000H
00000H
0
(Up count by BSCLK) nA1 0FFFB50H
k
(Up count by RCCLK(RS0)) Counter B 000000H 000000H
l
nB0 (Up count by RCCLK(RT0))
1000000H-nB0
INT occurred
a
d
RC-ADC interrupt request
RADINT
e
s o
HLT
Over flow
p
INT occurred
〈
1st step
〉 〈
2nd step
〉
Note
）
nA0=4B0H
，
t
BSCLK
=1/32768Hz
，

～
s
：
software
，
a
～
f
：
hardware
Overflow
00H
01H (ERAD=1)