Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504 13–1
13 UART
13.1 General Description
This LSI includes one channel of UART (Universal Asynchronous Receiver Transmitter), a full-duplex
communication start-stop synchronous serial interface.
For input clocks, see Chapter 6, "Clock Generation Circuit".
To use the UART, it needs to set the secondary and quartic functions of the ports 0, 3, 4, and 5.
For the port
function setting, see Chapter 17 "Port 0", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port5".
If The UART is used, Set to "0" the both of DUA0 and DUA1 bit of BLKCON2 register. If the both of
these
bits are "1", the UART is reset-state. For BLKCON2 register, see Chapter 4, "Power Management”.
13.1.1 Features
•
5-bit/6-bit/7-bit/8-bit data length selectable.
•
Odd parity, even parity, or no parity selectable.
•
1 stop bit or 2 stop bits selectable.
•
Provided with parity error flag, overrun error flag, framing error flag, and transmit buffer status flag.
•
Positive logic or negative logic selectable as communication logic.
•
LSB first or MSB first selectable as a communication direction.
•
Communication speed: Settable within the range of 4800bps to 115200bps.
•
Built-in baud rate generator.
13.1.2 Configuration
Figure 13-1 shows the configuration of the UART.
UA0BUF : UART0 receive buffer
UA1BUF : UART0 transmit buffer
UA0BRTH,L : UART0 baud rate registers H and L
UA0CON : UART0 control register
UA0MOD : UART0 mode register
UA0STAT : UART0 receive status register
UA1STAT : UART0 transmit status register
UA1CON : UART0 transmit monitor register
Figure 13-1 Configuration of UART
UA0BUF
UA1BUF
Shift Register
UA0INT
UA1INT
Baud Rate
Generator
UA0CON
UA0MOD0,1
UART
Controller
TXD0
(P01/P31/P41/P51)
OSCLK
Data bus
UA0BRTH,L
LSCLK
RXD0
(P00/P30/P40/P50)
UA0STAT
UA1STAT
UA1CON