Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 2 CPU and Memory Space
FEUL620Q504 2–5
2.7 Multiplication/Division Coprocessor
2.7.1 General Description
This LSI has the built-in multiplication/division function as a coprocessor of the CPU nX-U16/100.
For the coprocessor instructions, see "nX-U16/100 Core Instruction Manual".
For the multiplication/division library including the routines that carry out operations using this function, see
"MULDIVU8LIB User's Manual".
• Signed or unsigned operation setting
• Multiplication: 16bit x 16bit (operation time 4 cycles)
• Division: 32bit / 16bit (operation time 8 cycles)
• Division: 32bit / 32bit (operation time 16 cycles)
• Multiply-accumulate (non-saturating): 16bit x 16bit + 32bit (operation time 4 cycles)
• Multiply-accumulate (saturating): 16bit x 16bit + 32bit (operation time 4 cycles)
• In a saturating multiply-accumulate operation, the result is fixed to 7FFF_FFFFH for a positive number
and 8000_0000H for a negative number when it is out of the expressible range.
2.7.2 List of Registers
These are byte type registers for carrying out operations.
Though the registers are in byte length, consecutive registers can be accessed as a word type register (ERn), double
word type register (XRn), or quad type register (QRn) by combining them using different addressing modes.
Name
Symbol
(Quad-Word)
Symbol
(Double-Word)
Symbol
(Word)
Symbol
(Byte)
R/W Size
Initial value
[H]
A register L
CQR0
CXR0
CER0
CR0 R/W 8 00
A register H CR1 R/W 8 00
B register L
CER2
CR2 R/W 8 00
B register H CR3 R/W 8 00
C register L
CXR4
CER4
CR4 R/W 8 00
C register H CR5 R/W 8 00
D register L
CER6
CR6 R/W 8 00
D register H CR7 R/W 8 00
Operation mode register
CQR8
CXR8
CER8
CR8 R/W 8 00
Operation status register CR9 R/W 8 00
–
CER10
CR10 - - 00
– CR11 - - 00
–
CXR12
CER12
CR12 - - 00
– CR13 - - 00
–
CER14
CR14 - - 00
Coprocessor ID register CR15 R 8 81
CR10 to CR14 have no function. Reading them gives "00H". Writing is ignored.