Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–11
5.2.5 Interrupt Enable Register 67 (IE67)
Address: 0F016H
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7 6 5 4 3 2 1 0
IE6 – – – – EFTM3 EFTM2 EFTM1 EFTM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
IE7 – – – – – ELTBC2 ELTBC1 ELTBC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IE67 is a special function register (SFR) used to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of
IE67 is not reset.
Description of Bits
•
EFTM0 (bit 0)
EFTM0 is the enable flag for the 16-bit timer 0 interrupt (FTM0INT).
EFTM0 Description
0 Disabled (initial value)
1 Enabled
•
EFTM1 (bit 1)
EFTM1 is the enable flag for the 16-bit timer 1 interrupt (FTM1INT).
EFTM1 Description
0 Disabled (initial value)
1 Enabled
•
EFTM2 (bit 2)
EFTM2 is the enable flag for the 16-bit timer 2 interrupt (FTM2INT).
EFTM1 Description
0 Disabled (initial value)
1 Enabled
•
EFTM3 (bit 3)
EFTM3 is the enable flag for the 16-bit timer 3 interrupt (FTM3INT).
EFTM3 Description
0 Disabled (initial value)
1 Enabled