Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–7
Chapter 14
14. UART with FIFO (UARTF) ............................................................................................................ 14-1
14.1 General Description
................................................................................................................
14-
1
14.1.1 Features .................................................................................................................. 14-1
14.1.2 Configuration ........................................................................................................... 14-2
14.1.3 List of Pins .............................................................................................................. 14-3
14.2 Description of Registers .......................................................................................................... 14- 3
14.2.1 List of Registers ...................................................................................................... 14-3
14.2.2 UARTF0 Transmit/Receive Buffer (UAF0BUF) ...................................................... 14-4
14.2.3 UARTF0 Interrupt Enable Register (UAF0IER) ...................................................... 14-5
14.2.4 UARTF0 Interrupt Status Register (UAF0IIR) ........................................................ 14-6
14.2.5 UARTF0 Mode Register (UAF0MOD) .................................................................... 14-8
14.2.6 UARTF0 Line Status Register (UAF0LSR) .......................................................... 14-11
14.2.7 UARTF0 Clock Adjustment Register (UAF0CAJ) ................................................ 14-14
14.2.8 UARTF0 Interrupt Request Register (UAF0IRQ) ................................................. 14-15
14.3 Description of Operation ....................................................................................................... 14- 16
14.3.1 Data Transmission ................................................................................................ 14-16
14.3.2 Data Reception ..................................................................................................... 14-17
14.3.3 Baud Rate Clock Generation ................................................................................ 14-19
14.3.4 FIFO Mode ............................................................................................................ 14-20
14.3.5 FIFO Polled Mode ................................................................................................. 14-21
14.3.6 Error Status ........................................................................................................... 14-22
14.3.7 Reset By Block Control Register .......................................................................... 14-23
Chapter 15
15. I
2
C Bus Interface ........................................................................................................................... 15-1
15.1 General Description ................................................................................................................ 15- 1
15.1.1 Features .................................................................................................................. 15-1
15.1.2 Configuration ........................................................................................................... 15-1
15.1.3 List of Pins .............................................................................................................. 15-1
15.2 Description of Registers
..........................................................................................................
15-
2
15.2.1 List of Registers ...................................................................................................... 15-2
15.2.2 I
2
C Bus n Receive Data Register (I2CnRD : n=0,1) ............................................... 15-3
15.2.3 I
2
C Bus n Slave Address Register (I2CnSA : n=0,1) .............................................. 15-4
15.2.4 I
2
C Bus n Transmit Data Register (I2CnTD : n=0,1) .............................................. 15-5
15.2.5 I
2
C Bus n Control Register (I2CnCON : n=0,1) ...................................................... 15-6
15.2.6 I
2
C Bus n Mode Register (I2CnMOD : n=0,1) ........................................................ 15-8
15.2.7 I
2
C Bus n Status Register (I2CnSTAT : n=0,1) .................................................... 15-10
15.3 Description of Operation
.......................................................................................................
15-
11
15.3.1 Communication Operation Mode .......................................................................... 15-11
15.3.1.1 Start Condition
...............................................................................................
15-
11
15.3.1.2 Restart Condition
...........................................................................................
15-
11
15.3.1.3 Slave Address Transmit Mode ..................................................................... 15- 11
15.3.1.4 Data Transmit Mode ...................................................................................... 15- 11
15.3.1.5 Data receive mode ........................................................................................ 15- 11
15.3.1.6 Control Register Setting Wait State ............................................................. 15- 12
15.3.1.7 Stop Condition
...............................................................................................
15-
12
15.3.2 Communication Operation Timing ........................................................................ 15-13
15.3.3 Operation Waveforms ........................................................................................... 15-15
15.3.4 Pin Settings ........................................................................................................... 15-16