ML620Q503/Q504 User's Manual
Chapter 2 CPU and Memory Space
FEUL620Q504 2–2
2.2 Program Memory Space
The program memory space stores program codes or vector tables.
The program codes have a length of 16 bits and are specified by a 16-bit program counter (PC).
The program memory space is configured by 32K words (64Kbytes) as one segment (code segment).
The vector table defines the entry address of the program executed at reset and interrupt and is placed in the
segment 0's 0H to 0FEH.
The program memory space capacity determines the memory model. The ML620Q503 and ML620Q504 having
a program memory space of 64Kbytes supports the small model. For details of memory model, see "nX-U16/100
Core Instruction Manual".
Figures 2-1 show the configuration of the program memory space.
CSR:PC
Code segment 0
0:0000H
Vector table
or
Program code
0:00FFH
0:0100H
Program code
0:7BFFH
0:7C00H
Test data
area
(Rewritable)
0:7DFFH
0:7E00H
Test data
area
(Not rewritable)
0:7FFFH
8bit
(a) ML620Q503 Configuration of Program Memory Space
Code segment 0
0:0000H
Vector table
or
Program code
0:00FFH
0:0100H
Program code
0:0FBFFH
0:0FC00H
Test data
area
(Rewritable)
0:0FDFFH
0:0FE00H
Test data
area
(Not rewritable)
0:0FFFFH
8bit
(b) ML620Q504 Configuration of Program Memory Space
Figure 2-1 Configuration of Program Memory Space
[Note]
• A program code cannot be placed in the test data area (1KB).
When rewriting the content of program memory space, ensure to write "0FFH" in the test data area. If data
in the area is uncertain or other data (i.e. not 0FFH), operating with the code cannot be guaranteed.
• It is recommended that the "0FFH" data (BRK instruction) is set in the unused area of the program memory
space as a fail-safe.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...