Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 8 Timers
FEUL620Q504 8–5
8.2.3 Timer n Counter Register (TMnmC : {n,m}={0,1} , {2,3} , {4,5} , {6,7})
Address: 0F310H(TM0C/TM01C), 0F311H(TM1C), 0F312H(TM2C/TM23C), 0F313H(TM3C),
0F314H(TM4C/TM45C), 0F315H(TM5C), 0F316H(TM6C/TM67C), 0F317H(TM7C)
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
TMnC TnC7 TnC6 TnC5 TnC4 TnC3 TnC2 TnC1 TnC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
TMmC TmC7 TmC6 TmC5 TmC4 TmC3 TmC2 TmC1 TmC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TMnC is a special function register (SFR) that functions as an 8-bit binary counter.
When write random data to TMnC (TMmC), TMnC is cleared to “00H”.
In 16-bit timer mode, the combination becomes “TM0C and TM1C”, “TM2C and TM3C”, “TM4C and TM5C” and
“TM6C and TM7C”.
Even if write to either Low-order(TM0C,TM2C,TM4C,TM6C) timer counter or high-order
(TM1C,TM3C,TM5C,TM7C) timer counter, both timer counters are cleared to “00H”.
Case of a combination of Timer clock and System clock shown in Table 8-1, able to read the TMnC even during
operation.
Table 8-1 TMnC Read Enable condition during Timer Operation
System clock
SYSCLK
Timer clock
TnCK
LSCLK
LSCLK and divided LSCLK
However, except for Timer6,7 low-speed crystal oscillator
selection.
HSCLK
OSCLK and divided OSCLK
However, when frequency of SYSCLK is more than TnCK