ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-22
14.3.6 Error Status
(a)
Overrun error
An overrun error indicates that the data in RBR was not read before the next character was sent to RBR to
overwrite the previous character.
At this time, UF0OER of UAF0LSR is set.
(b)
Parity error
A parity error indicates that the parity of the received data and the received parity bit did not match. At this
time, UF0PER of UAF0LSR is set.
Note that, this error will only occur when parity is enabled.
In FIFO mode, this bit indicates that an error exists for the leading data. If a parity error occurs in the data
that is not the leading data in the FIFO, it is not reflected to UF0PER of UAF0LSR.
(c)
Framing error
A framing error indicates that there is no valid stop bit in the received character. This error will occur when
the stop bit after the last data bit or after the parity bit is "0" (spacing level).
At this time, UF0FER of UAF0LSR is set.
In FIFO mode, this is related to a specific character in the FIFO. UF0FER indicates that an error is present
when that character comes to the beginning of the FIFO.
(d)
Break interrupt
A break interrupt indicates that the input data received was maintained in the spacing ("0") state during the
transmission of one frame (start bit + data bit + parity bit + stop bit).
At this time, UF0BI of the UAF0LSR register is set.
In FIFO mode, this is related to a specific character in the FIFO. UF0BI indicates that the break character is
present at the beginning of the FIFO.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...