ML620Q503/Q504 User’s Manual
Chapter 18 Port 1
FEUL620Q504 18–5
18.2.4 Port 1 Control Register (P1CON)
Address: 0F21AH
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7
6
5
4
3
2
1
0
P1CON0
–
–
–
–
–
–
P11C0
P10C0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
P1CON1
–
–
–
–
–
–
P11C1
P10C1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
P1CON0 and P1CON1 are special function registers (SFRs) to select input/output state of the Port 1 pin. The
input/output state is different between input mode and output mode. Input or output is selected by using the P1DIR
register.
Description of Bits
•
P11-10C0
(bits 1 to 0)
, P11-00C1
(bits 9 to 8)
The P11-10C1 pins and the P11-10C0 pins are used to select high-impedance output, P-channel open drain output,
N-channel open drain output, or CMOS output in output mode and to select high-impedance input, input with a
pull-down resistor, or input with a pull-up resistor in input mode.
Setting of P10 pin
Description
P10C1
P10C0
When output mode selected
(P10DIR = 0)
When input mode selected
(P10DIR = 1)
0
0
P10 pin: High-impedance output (initial
value)
P10 pin: high-impedance input
mode (initial value)
0
1
P10 pin: P-channel open drain output
P10 pin: input mode with a
pull-down resistor
1
0
P10 pin: N-channel open drain output
P10 pin: input mode with a pull-up
resistor
1
1
P10 pin: CMOS output
P10 pin: high-impedance input
mode
Setting of P11 pin
Description
P11C1
P11C0
When output mode selected
(P11DIR = 0)
When input mode selected
(P11DIR = 1)
0
0
P11 pin: High-impedance output (initial
value)
P11 pin: high-impedance input
mode (initial value)
0
1
P11 pin: P-channel open drain output
P11 pin: input mode with a
pull-down resistor
1
0
P11 pin: N-channel open drain output
P11 pin: input mode with a pull-up
resistor
1
1
P11 pin: CMOS output
P11 pin: high-impedance input
mode
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...