ML620Q503/Q504 User's Manual
Chapter 21 Port 4
FEUL620Q504 21-14
21.3 Description of Operation
21.3.1 Input/Output Port Functions
For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR).
In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output
mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and
P4CON1).
In the input mode, set the port 4 control registers 0 and 1 (P4CON0 and P4CON1) to select any of
high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor.
At a system reset, high-impedance output mode is selected as the initial status.
In output mode, “L” or “H” level is output to each pin of Port 4 depending on the value set by the Port 4 data
register (P4D).
In input mode, the input level of each pin of Port 4 can be read from the Port 4 data register (P4D).
21.3.2 Primary Function Other Than Input/Output Port
The external interrupt input (EXI40 to EXI47) can be assigned to the port 4 as the primary function other than
the input/output port.
21.3.3 Secondary to Quartic Functions
The I2C bus pin (SDA0/1, SCL0/1), Melody/Buzzer output (MD0), low speed clock(LSCLKO), high speed
clock (OUTCLK), synchronous serial port pin (SIN0, SCK0, SOUT0), synchronous serial port with FIFO pin
(SINF0, SCKF0, SOUTF0, SSF0), UART pin (RXD0, TXD0), UART with FIFO pin (RXDF0, TXDF0), and
timer out output pin (TMOUT8/9/A/B) are assigned to the port 4 as the secondary, tertiary, or quartic function.
Each of them can be used as the secondary, tertiary or quartic function by setting the P47MD0 to P40MD0 and
P47MD1 to P40MD1 bits of the port 4 mode register (P4MOD0, P4MOD1).
Output frequency of High speed clock output can be selected by frequency control register 0 (FCON0) OUTC2
to OUTC0. See Chapter 6 “Clock Generation Circuit”.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...