Control Registers
269
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
5.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see
.
The error address is captured during errors when either EOFEN or EZFEN enable bit is set. During error
profiling mode when only EPEN is set, the error address is not captured if a correctable error is detected.
This register is frozen while either the ERR_ZERO_FLG or the ERR_ONE_FLG bit is set in the
FEDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit (see
), this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-12. Flash Correctable Error Address Register (FCOR_ERR_ADD) [offset = 14h]
31
16
COR_ERR_ADD
R-u
15
3
2
0
COR_ERR_ADD
B_OFF
R-u
R-u
LEGEND: R = Read only; -
n
= value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-17. Flash Correctable Error Address Register (FCOR_ERR_ADD) Field Descriptions
Bit
Field
Value
Description
31-3
COR_ERR_ADD
0-1FFF FFFFh
Correctable Error Address
COR_ERR_ADD records the CPU logical address of which a correctable error is
detected by the ECC logic. This error address is frozen from begin updated until it is
read by the CPU. Additional error are blocked until this register is read.
2-0
B_OFF
0-7h
Byte Offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the
address captured is aligned to a 64-bit boundary with address bits[2:0] equal to
0.When reading from the ECC bytes, these bits will indicate the failing address of the
ECC location associated with the failure. When reading an ECC byte, the ECC is
checked against the 64 data bits they protect.
