C O U N T
C A P T U R E
S S W
C O U N T
C L K O U T
S S W
O D
N R
N F
_
_
_
_
=
´
PLL
383
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
10.5.6 PLL Frequency Measurement Circuit
The same circuit that is used to measure modulation depth is also available to measure the average
frequency of the PLL. In this mode, the PLL output (before the R-divider) is captured in
SSW_CLKOUT_COUNT while the oscillator is captured in SSW_CAPTURE_COUNT. The procedure for
using the PLL frequency measurement circuit is:
1. While the PLL is enabled, set EXT_COUNTER_EN.
2. Set COUNTER_EN. This bit clears both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and
then immediately enables for counting.
3. Wait for some software delay loop.
4. Clear COUNTER_EN. Wait for COUNTER_READ_READY to set. Read both
SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and compute the ratio of PLL multiplication
as:
(13)
5. Note that CAPTURE_WINDOW_INDEX, COUNTER_RESET, TAP_COUNTER_DIS are not used in
this procedure.
10.5.7 PLL2
PLL2 drives GCM clock source 6.
The PLL is identical to PLL1, except modulation is disabled on this instance of the PLL. Also, the PLL
typically does not clock the system, there is no automatic switch over feature. Any PLL error can be
handled by the CPU.
PLL2 is programmed through PLLCTL3.
