VCLK
Write to enable
MINTIGENA key
Write to enable
MSINENAn
SYS_MMISTARTn
DEV_MMIDONEn
Memory
(where n = 31:0)
(where n = 31:0)
(where n = 31:0)
Poll MINIDONE bit,
MSTCGSTAT[8]
Poll MIDONEn field of
When each enabled module completes
corresponding MIIDONE bit is set.
After all enabled modules’ hardware initialization
completes, the MINIDONE bit is set, indicating
all hardware memory initialization is done.
(where n = 31:0)
module
hardware
initialization
Black indicates System register activity.
Gray indicates inter-module activity, not accessible via System register.
its hardware initialization, the
(from System module
to memory modules)
(from memory modules
to System module)
MINISTAT register
Memory Organization
109
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.2.4.2
Auto-Initialization of On-Chip SRAM Modules
The device system provides the capability to perform a hardware initialization on most memories on the
system bus and on the peripheral bus.
The intent of having the hardware initialization is to program the memory arrays with error detection
capability to a known state based on their error detection scheme – odd/even parity or ECC. For example,
the contents of the CPU data RAM after power-on reset is unknown. A hardware auto-initialization can be
started to that there is no ECC error.
NOTE:
Effect of ECC or Parity on Memory Auto-Initialization
The ECC or parity should be enabled on the RAMs before hardware auto-initialization starts
if parity or ECC is being used.
Auto-Initialization Sequence:
1. Enable the global hardware memory initialization key by programming 0xA into MINITGCR[3:0], the
Memory Initialization Key field (MINITGENA) of the Memory Hardware Initialization Global Control
Register (MINITGCR) register.
2. Select the module on which the memory hardware initialization has to be performed by programming
the appropriate value into the MSINENA(31–0) bits in the MSINENA register. See
.
3. If the global auto-initialization scheme is enabled, the corresponding module will initialize its memories
based on its memory error checking scheme (even parity or odd parity or ECC).
4. When the memory initialization is complete, the module will signal “memory initialization done”, which
sets the corresponding bit in the system module MIDONE field of the MINISTAT register to indicate the
completion of its memory initialization.
5. When the memory hardware initialization completes for all modules, (indicated by each module’s
MIDONE bit being set), the memory hardware initialization done bit (MINIDONE) is set in the
MSTCGSTAT register.
Figure 2-3. Hardware Memory Initialization Protocol
