Overview
1118
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.1 Overview
The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
The SPI has the following attributes:
•
16-bit shift register
•
Receive buffer register
•
11-bit baud clock generator
•
Serial clock (SPICLK) pin
•
1 SPISOMI/SPISIMO pin for data transfer, with programmable pin direction
•
SPI enable (SPIENA) pin
•
Up to 6 slave chip select (SPICS) pins
•
SPICLK can be internally-generated (and driven) or received from an external clock source
•
Each word transferred can have a unique format
•
SPI pins can be used as functional or digital Input/Output pins (GIOs)
NOTE:
SIMO - Slave In Master Out Pin
SOMI - Slave Out Master In Pin
SPICS - SPI Chip Select Pin
SPIENA - SPI Enable Pin
24.1.1 Word Format Options
Each word transferred can have a unique format. Several format characteristics are programmable for
each word transferred:
•
SPICLK frequency
•
Character length (2 to 16 bits)
•
Phase (with and without delay)
•
Polarity (high or low)
•
Parity enabled/disabled
•
Chip Select(CS) timers for setup and hold
•
Shift direction (Most-Significant Bit (MSB) first or Least-Significant Bit (LSB) first)
•
Multi-pin parallel modes
24.1.2 Multi-buffering (Mib) Support
The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
without CPU intervention. The buffers are combined in different Transfer Groups (TGs) that can be
triggered by external events (timers, Input/Output activity, and so on) or by the internal tick counter. The
internal tick counter supports periodic trigger events. Each buffer of the MibSPI can be associated with
different DMA channels in different TGs, allowing the user to move data between internal memory and an
external slave with minimal CPU interaction.
