Control Registers
1207
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.9.42 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR)
In multi-buffer mode, if a particular RXRAM location is written by the MibSPI sequencer logic after the
completion of a new transfer when that location already contains valid data, the RX_OVR bit will be set to
1 while the data is being written. The RXOVRN_BUF_ADDR register captures the address of the RXRAM
location for which a receiver overrun condition occurred.
Figure 24-72. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]
31
16
Reserved
R-0
15
10
9
0
Reserved
RXOVRN_BUF_ADDR
R-0
R-200h
LEGEND: R = Read only; -
n
= value after reset
Table 24-50. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions
Bit
Field
Value
Description
31-10
Reserved
0
Reads return 0. Writes have no effect.
9-0
RXOVRN_BUF_ADDR
200h-3FCh
Address in RXRAM at which an overwrite occurred. This address value will show only
the offset address of the RAM location in the multi-buffer RAM address space. Refer
to the device-specific data sheet for the actual absolute address of RXRAM.
This word-aligned address can vary from 200h-3FCh. Contents of this register are
valid only when any of the INTVECT0 or INTVECT1 and SPIFLG registers show an
RXOVRN error vector while in multi-buffer mode. If there are multiple overrun errors,
then this register holds the address of first overrun address until it is read.
Note: Reading this register clears the RXOVRN interrupt flag in the SPIFLG
register and the TGINTVECTx.
Note: Receiver overrun errors in multi-buffer mode can be completely avoided
by using the SUSPEND until RXEMPTY feature, which can be programmed into
each buffer of any TG. However, using the SUSPEND until RXEMPTY feature will
make the sequencer wait until the current RXRAM location is read by the VBUS
master before it can start the transfer for the same buffer location again. This
may affect the overall throughput of the SPI transfer. By enabling the interrupt
on RXOVRN in multi-buffer mode, the user can rely on interrupts to know if a
receiver overrun has occurred. The address of the overrun in RXRAM is
indicated in this RXOVRN_BUF_ADDR register.