Texas Instruments RM48 series, Technical Reference Manual

Page: 1729 / 1759

www.ti.com
Control Registers
1729 SPNU503C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
31.4.13 RTP Pin Control 5 Register (RTPPC5)
This register provides the option to set pins to a logic 0 level without influencing the state of other pins. It
eliminates the read-modify-write operation necessary with
RTPPC3 . Once the pin is configured in
functional mode ( RTPPC0 ), setting the corresponding bit to one in RTPPC5 will not affect the pinstate.
Figure 31-21 and Table 31-21 illustrate this register.
Figure 31-21. RTP Pin Control 5 Register (RTPPC5) [offset = 48h]
31 19 18 17 16
Reserved ENACLR CLKCLR SYNCCLR
R-0 R/W-0 R/W-0 R/W-0
15 0
DATACLR[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 31-21. RTP Pin Control 5 Register (RTPPC5) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Read returns 0. Writes have no effect.
18 ENACLR Sets the output state of RTPENA pin to logic low. Value in the ENASET bit sets the data output
control register bit to 0, regardless of the current value in the ENAOUT bit .
User and privilege mode (read):
0 The pin is configured to output a logic low (0) (output voltage is V
OL
or lower).
1 The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
0 Writing a zero to this bit has no effect.
1 Set pin to logic low (0) (output voltage is V
OL
or lower).
17 CLKCLR Sets output state of RTPCLK pin to logic low. Value in the CLKCLR bit sets the data output control
register bit to 0, regardless of the current value in the CLKOUT bit
User and privilege mode (read):
0 The pin is configured to output a logic low (0) (output voltage is V
OL
or lower).
1 The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
0 Writing a zero to this bit has no effect.
1 Set pin to logic low (0) (output voltage is V
OL
or lower).
16 SYNCCLR Sets output state of RTPSYNC pin logic low. Value in the SYNCCLR bit clears the data output
control register bit to 0, regardless of the current value in the SYNCOUT bit.
User and privilege mode (read):
0 The pin is configured to output a logic low (0) (output voltage is V
OL
or lower).
1 The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
0 Writing a zero to this bit has no effect.
1 Set pin to logic low (0) (output voltage is V
OL
or lower).
15-0 DATACLR[ n ] Sets output state of RTPDATA[15:0] pins to logic low. Value in the DATAxCLR bit clears the data
output control register bit to 0, regardless of the current value in the DATAxOUT bit. Each bit [ n ]
represents a single pin.
User and privilege mode (read):
0 The pin is configured to output a logic low (0) (output voltage is V
OL
or lower).
1 The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
0 Writing a zero to this bit has no effect.
1 Set pin to logic low (0) (output voltage is V
OL
or lower).