Texas Instruments RM48 series, Technical Reference Manual

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STC Test Coverage and Duration
347 SPNU503C – March 2018
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CPU Self-Test Controller (STC) Module
8.3 STC Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval when the device is
running at HCLK = 180 MHz, VCLK = 90 MHz, and STCCLK = 90 MHz are shown in
Table 8-1 .
Table 8-1. STC Test Coverage and Duration
Intervals Test Coverage (%) Test Time (Cycles) Test Time (µs)
0 0 0 0
1 62.13 1365 15.17
2 70.09 2730 30.33
3 74.49 4095 45.50
4 77.28 5460 60.67
5 79.28 6825 75.83
6 80.90 8190 91.00
7 82.02 9555 106.17
8 83.10 10920 121.33
9 84.08 12285 136.50
10 84.87 13650 151.67
11 85.59 15015 166.83
12 86.11 16380 182.00
13 86.67 17745 197.17
14 87.16 19110 212.33
15 87.61 20475 227.50
16 87.98 21840 242.67
17 88.38 23205 257.83
18 88.69 24570 273.00
19 88.98 25935 288.17
20 89.28 27300 303.33
21 89.50 28665 318.50
22 89.76 30030 333.67
23 90.01 31395 348.83
24 90.21 32760 364.00
Table 8-2 gives the typical STC execution times for 24 intervals at different clock rates.
Table 8-2. Typical STC Execution Times
Number of Intervals @ HCLK = 180 MHz
VCLK = 90 MHz
STCCLK = 90 MHz
@ HCLK = 100 MHz
VCLK = 100 MHz
STCCLK = 50MHz
@ HCLK = 160 MHz
VCLK = 80 MHz
STCCLK = 80 MHz
24 364 µs 655.20 µs 409.50 µs