SCI Control Registers
1344
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI) Module
26.7.3 SCI Set Interrupt Register (SCISETINT)
and
illustrate this register. SCISETINT register is used to enable the required
interrupts supported by the module.
Figure 26-10. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch]
31
27
26
25
24
Reserved
SET FE INT
SET OE INT
SET PE INT
R-0
R/W-0
R/W-0
R/W-0
23
19
18
17
16
Reserved
SET RX DMA
ALL
SET RX DMA
SET TX DMA
R-0
R/WC-0
R/W-0
R/W-0
15
10
9
8
Reserved
SET RX INT
SET TX INT
R-0
R/W-0
R/W-0
7
2
1
0
Reserved
SET WAKEUP
INT
SET BRKDT
INT
R-0
R/W-0
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; WC = Write in sci-compatible mode only; -
n
= value after reset
Table 26-6. SCI Set Interrupt Register (SCISETINT) Field Descriptions
Bit
Field
Value
Description
31-27
Reserved
0
Reads return 0. Writes have no effect.
26
SET FE INT
Set framing-error interrupt. Setting this bit enables the SCI module to generate an interrupt
when a framing error occurs.
0
Read:
The interrupt is disabled.
Write:
Writing a 0 to this bit has no effect.
1
Read or write:
The interrupt is enabled.
25
SET OE INT
Set overrun-error interrupt. Setting this bit enables the SCI module to generate an interrupt
when an overrun error occurs.
0
Read:
The interrupt is disabled.
Write:
Writing a 0 to this bit has no effect.
1
Read or write:
The interrupt is enabled.
24
SET PE INT
Set parity interrupt. Setting this bit enables the SCI module to generate an interrupt when a
parity error occurs.
0
Read:
The interrupt is disabled.
Write:
Writing a 0 to this bit has no effect.
1
Read or write:
The interrupt is enabled.
23-19
Reserved
0
Reads return 0. Writes have no effect.
18
SET RX DMA ALL
Set receive DMA all. This bit determines if a separate interrupt is generated for the address
frames sent in multiprocessor communications. When this bit is 0, RX interrupt requests are
generated for address frames and DMA requests are generated for data frames. When this bit
is 1, RX DMA requests are generated for both address and data frames.
0
Read:
The DMA request is disabled for address frames (the receive interrupt request is enabled
for address frames).
Write:
Writing a 0 to this bit has no effect.
1
Read and write:
The DMA request is enabled for address and data frames
17
SET RX DMA
Set receiver DMA. To enable receiver DMA requests, this bit must be set. If it is cleared,
interrupt requests are generated depending on the SET RX INT bit (SCISETINT[9]).
0
Read:
The DMA request is disabled.
Write:
Writing a 0 to this bit has no effect.
1
Read and write:
The DMA request is enabled for address and data frames
