Memory
Configurations,
Algorithms,
Backgrouns
Host CPU
Control Interface
System
and
Peripheral
Memories
Data Logger
PBIST
Controller
Memory
Data
Path
PBIST
ROM
Overview
321
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Programmable Built-In Self-Test (PBIST) Module
7.1
Overview
The PBIST (Programmable Built-In Self-Test) controller architecture provides a run-time-programmable
memory BIST engine for varying levels of coverage across many embedded memory instances.
7.1.1 Features of PBIST
•
Information regarding on-chip memories, memory groupings, memory background patterns and test
algorithms stored in dedicated on-chip PBIST ROM
•
Host processor interface to configure and start BIST of memories
•
Supports testing of PBIST ROM itself as well
•
Supports testing of each memory at its maximum access speed in application
•
Implements intelligent clock gating to conserve power
NOTE:
Refer to the device datasheet for the maximum PBIST ROM clock frequency supported.
7.1.2 PBIST vs. Application Software-Based Testing
The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted
specifically toward testing memories. This coprocessor executes test routines stored in the PBIST ROM
and runs them on multiple on-chip memory instances. The on-chip memory configuration information is
also stored in the PBIST ROM. The testing is done in parallel for each of the CPU data RAMs, while it is
done sequentially for the rest of the memories.
The PBIST Controller architecture offers significant advantages over tests running on the main Cortex-
R4F processor (application software-based testing):
•
Embedded CPUs have a long access path to memories outside the tightly-couple memory sub-system,
while the PBIST controller has a dedicated path to the memories specifically for the self-test
•
Embedded CPUs are designed for their targeted use and are often not easily programmed for memory
test algorithms.
•
The memory test algorithm code on embedded CPUs is typically significantly larger than that needed
for PBIST.
•
The embedded CPU is significantly larger than the PBIST controller.
7.1.3 PBIST Block Diagram
illustrates the basic PBIST blocks and its wrapper logic for the device.
Figure 7-1. PBIST Block Diagram
