EMIF Registers
651
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)
The asynchronous wait cycle configuration register (AWCC) is used to configure the parameters for
extended wait cycles. Both the polarity of the EMIF_nWAIT pin(s) and the maximum allowable number of
extended wait cycles can be configured. The AWCC is shown in
and described in
. Not all devices support both EMIF_nWAIT[1] and EMIF_nWAIT[0], see the device-specific data
manual to determine support on each device.
NOTE:
The EW bit in the asynchronous
n
configuration register (CE
n
CFG) must be set to allow for
the insertion of extended wait cycles.
Figure 17-16. Asynchronous Wait Cycle Configuration Register (AWCCR) [offset = 04h]
31
30
29
28
27
24
23
22
21
20
19
18
17
16
Reserved
WP1
WP0
Reserved
CS5_WAIT
CS4_WAIT
CS3_WAIT
CS2_WAIT
R-3h
R/W-1
R/W-1
R-0
R/W-0
R/W-0
R/W-0
R/W-0
15
8
7
0
Reserved
MAX_EXT_WAIT
R-0
R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 17-26. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
Bit
Field
Value
Description
31-30
Reserved
3h
Reserved
29
WP1
EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin.
0
Insert wait cycles if EMIF_nWAIT[1] pin is low.
1
Insert wait cycles if EMIF_nWAIT[1] pin is high.
28
WP0
EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin.
0
Insert wait cycles if EMIF_nWAIT[0] pin is low.
1
Insert wait cycles if EMIF_nWAIT[0] pin is high.
27-24
Reserved
0
Reserved
23-22
CS5_WAIT
0-3h
Chip Select 5 WAIT signal selection. This signal determines which EMIF_nWAIT[
n
] signal will
be used for memory accesses to chip select 5 memory space. This device does not support
chip select 5, so any value written to this field has no effect.
21-20
CS4_WAIT
Chip Select 4 WAIT signal selection. This signal determines which EMIF_nWAIT[
n
] signal will
be used for memory accesses to chip select 4 memory space.
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
2h-3h
Reserved
19-18
CS3_WAIT
Chip Select 3 WAIT signal selection. This signal determines which EMIF_nWAIT[
n
] signal will
be used for memory accesses to chip select 3 memory space.
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
2h-3h
Reserved
17-16
CS2_WAIT
Chip Select 2 WAIT signal selection. This signal determines which EMIF_nWAIT[
n
] signal will
be used for memory accesses to chip select 2 memory space.
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
2h-3h
Reserved
15-8
Reserved
0
Reserved
7-0
MAX_EXT_WAIT
0-FFh
Maximum extended wait cycles. The EMIF will wait for a maximum of (MAX_EX 1) ×
16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold
period of the access.
