Module Operation
394
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Dual-Clock Comparator (DCC) Module
11.2 Module Operation
As shown in
, the DCC contains two counters – counter0 and counter1, which are driven by
two signals – clock0 and clock1. The application programs the seed values for both these counters. The
application also configures the tolerance window time by configuring the valid counter for clock0.
Counter0 and counter1 both start counting simultaneously once the DCC is enabled. When counter0
counts down to zero, this automatically triggers the count down of the tolerance window counter (valid0).
The DCC module can be used in two different operating modes:
11.2.1 Continuous Monitoring Mode
In this mode, the DCC is used by the application to ensure that two clock signals maintain the correct
frequency ratio. Suppose the application wants to ensure that the PLL output signal (clock source # 1)
always maintains a fixed frequency relationship with the main oscillator (clock source # 0).
•
In this case, the application can use the main oscillator as the clock0 signal (for counter0 and valid0)
and the PLL output as the clock1 (for counter1).
•
The seed values of counter0, valid0 and counter1 are selected such that if the actual frequencies of
clock0 and clock1 are equal to their expected frequencies, then the counter1 will reach zero either at
the same time as counter0 or during the count down of the valid0 counter.
•
If the counter1 reaches zero during the count down of the valid0 counter, then all the counters
(counter0, valid0, counter1) are reloaded with their initial seed values once valid0 has also counted
down to zero.
•
This sequence of counting down and checking then continues as long as there is no error, or until the
DCC module is disabled.
•
The counters also all get reloaded if the application resets and restarts the DCC module.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that clock1 is faster than
expected, or clock0 is slower than expected. It includes the case when clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that
clock1 is slower than expected. It includes the case when clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application may then read out the counter values
to help determine what caused the error.
11.2.1.1 Error Conditions
While operating in continuous mode, the counters get reloaded with the seed values and continue
counting down under the following conditions:
•
The module is reset or restarted by the application, OR
•
Counter0, Valid 0 and Counter1 all reach 0 without any error
