16 SCI baud clock periods/bit
Majority
vote
LSB of data
Start bit
LINRX
Falling edge
detected
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 161 2 3 4 5
SCI Communication Formats
1235
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
25.2.2 SCI Timing Mode
The SCI can be configured to use asynchronous or isosynchronous timing using TIMING MODE bit in
SCIGCR1 register.
25.2.2.1 Asynchronous Timing Mode
The asynchronous timing mode uses only the receive and transmit data lines to interface with devices
using the standard universal asynchronous receiver- transmitter (UART) protocol.
In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods. Each
bit therefore consists of 16 samples (one for each clock period). When the SCI is using asynchronous
mode, the baud rates of all communicating devices must match as closely as possible. Receive errors
result from devices communicating at different baud rates.
With the receiver in the asynchronous timing mode, the SCI detects a valid start bit if the first four samples
after a falling edge on the LINRX pin are of logic level 0. As soon as a falling edge is detected on LINRX,
the SCI assumes that a frame is being received and synchronizes itself to the bus.
To prevent interpreting noise as Start bit SCI expects LINRX line to be low for at least four contiguous SCI
baud clock periods to detect a valid start bit. The bus is considered idle if this condition is not met. When a
valid start bit is detected, the SCI determines the value of each bit by sampling the LINRX line value
during the seventh, eighth, and ninth SCI baud clock periods. A majority vote of these three samples is
used to determine the value stored in the SCI receiver shift register. By sampling in the middle of the bit,
the SCI reduces errors caused by propagation delays and rise and fall times and data line noises.
illustrates how the receiver samples a start bit and a data bit in asynchronous timing mode.
The transmitter transmits each bit for a duration of 16 SCI baud clock periods. During the first clock period
for a bit, the transmitter shifts the value of that bit onto the LINTX pin. The transmitter then holds the
current bit value on LINTX for 16 SCI baud clock periods.
Figure 25-4. Asynchronous Communication Bit Timing
25.2.2.2 Isosynchronous Timing Mode
In isosynchronous timing mode, each bit in a frame has a duration of exactly 1 baud clock period and
therefore consists of a single sample. With this timing configuration, the transmitter and receiver are
required to make use of the SCICLK pin to synchronize communication with other SCI.
This mode is not
supported on this device because SCICLK pin is not available.
25.2.3 SCI Baud Rate
The SCI/LIN has an internally-generated serial clock determined by the peripheral VCLK and the
prescalers P and M in this register. The SCI uses the 24-bit integer prescaler P value of the BRS register
to select the required baud rates. The additional 4-bit fractional divider M refines the baud rate selection.
