EMIF Registers
658
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.3.9 EMIF Interrupt Masked Register (INTMSK)
Like the EMIF interrupt raw register (INTRAW), the EMIF interrupt masked register (INTMSK) is used to
monitor and clear the status of the EMIF’s hardware-generated Asynchronous Timeout Interrupt. The main
difference between the two registers is that when the AT_MASKED bit in this register is set, an active-high
pulse will be sent to the CPU interrupt controller. Also, the AT_MASKED bit field in INTMSK is only set to
1 if the associated interrupt has been enabled in the EMIF interrupt mask set register (INTMSKSET). The
EMIF on some devices does not have the EMIF_nWAIT pin, therefore, these registers and fields are
reserved on those devices. The INTMSK is shown in
and described in
Figure 17-23. EMIF Interrupt Mask Register (INTMSK) [offset = 44h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
WR_MASKED
LT_MASKED
AT_MASKED
R-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -
n
= value after reset
Table 17-33. EMIF Interrupt Mask Register (INTMSK) Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
2
WR_MASKED
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EMIF_nWAIT pin, provided that the WR_MASK_SET bit is set to 1 in the EMIF interrupt mask set
register (INTMSKSET).
0
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
1
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WR bit
in the EMIF interrupt raw register (INTRAW).
1
LT_MASKED
Masked Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line
size, only if the LT_MASK_SET bit in the EMIF interrupt mask set register (INTMSKSET) is set to 1.
0
Writing a 0 has no effect.
1
Writing a 1 will clear this bit as well as the LT bit in the EMIF interrupt raw register (INTRAW).
0
AT_MASKED
Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle, the EMIF_nWAIT pin did not go inactive within the number of
cycles defined by the MAX_EXT_WAIT field in the asynchronous wait cycle configuration register
(AWCC), provided that the AT_MASK_SET bit is set to 1 in the EMIF interrupt mask set register
(INTMSKSET).
0
Indicates that an Asynchronous Timeout Interrupt has not been generated. Writing a 0 has no
effect.
1
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit
as well as the AT bit in the EMIF interrupt raw register (INTRAW).
