Module Operation
561
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
Additional error handling is dependent on the requestor.
•
DMA reading from a control packet RAM: The transmission requested by DMA request will not take
place.
•
CPU reading from the control packet RAM: The data will be retrieved by the CPU and a parity error
interrupt will be generated.
In both cases, the control packet will be left active or the DMA will be switched off dependent on the
ERRA bit in the Parity Control Register (
16.2.16 Parity Testing
The parity RAM is accessible to allow manually inserting faults so that the parity checking feature can be
tested. Test mode is entered by asserting the TEST bit in the Parity Control Register (
).
Once the bit is set, the parity bits are mapped to the control packet RAM starting address A00h.
NOTE:
When in test mode, no parity checking will be done when reading from parity memory, but
parity checking will be performed on the normal memory.
Each byte in Control Packet RAM has its own parity bit in the Control Packet Parity RAM as shown in
,
, and
. P0 is the parity bit for byte 0, P1 is the parity bit for byte 1 and so
on.
Each byte in the control packet RAM has its own parity bit in the control packet parity RAM as shown in
and
Table 16-5. Control Packet RAM
Bit
31
24
23
16
15
8
7
0
Word0
Byte 0
Byte 1
Byte 2
Byte 3
Word1
Byte 4
Byte 5
Byte 6
Byte 7
Word2
Byte 8
Byte 9
Byte 10
Byte 11
Word3
Byte 12
Byte 13
Byte 14
Byte 15
Table 16-6. Control Packet RAM
Bit
127
96
95
64
63
32
31
0
Word 3
Word 2
Word 1
Word 0
Table 16-7. Parity RAM
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
16.2.17 Initializing RAM with Parity
After power up, the RAM content including the parity bit cannot be guaranteed. To avoid parity failures
when reading RAM, the RAM has to be initialized. The RAM can be initialized by writing known values into
it. When the known value is written, the corresponding parity bit will be automatically calculated and
updated.
Another possibility to initialize the memory is to follow the Auto-Initialization of On-Chip SRAM Modules
subsection in the
Architecture
chapter. The RAM will be initialized to 0. Depending on the even/odd parity
selection, the parity bit will be calculated accordingly.
To allow for parity calculation during initialization, the parity functionality has to be enabled as discussed in
