Texas Instruments RM48 series, Technical Reference Manual

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System and Peripheral Control Registers
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154 SPNU503C – March 2018
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Architecture
2.5.1.31 Clock Test Register (CLKTEST)
The CLKTEST register, shown in Figure 2-36 and described in Table 2-50 , controls the clock signal that is
supplied to the ECLK pin for test and debug purposes.
NOTE: Clock Test Register Usage
This register should only be used for test and debug purposes.
Figure 2-36. Clock Test Register (CLKTEST) [offset = 8Ch]
31 27 26 25 24
Reserved ALTLIMPCLOCK
ENABLE
RANGEDET
CTRL
RANGEDET
ENASSEL
R-0 R/WP-0 R/WP-0 R/WP-0
23 20 19 16
Reserved CLK_TEST_EN
R-0 R/WP-Ah
15 12 11 8 7 4 3 0
Reserved SEL_GIO_PIN Reserved SEL_ECP_PIN
R-0 R/WP-0 R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; - n = value after reset
Table 2-50. Clock Test Register (CLKTEST) Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Reads return 0. Writes have no effect.
26 ALTLIMPCLOCKENABLE This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock
monitor phase frequency detect (PFD).
0 The 10-MHz LPO fast clock is the compare clock for the clock detect PFD circuit and the
source to limp clock on a clock fail.
1 The ALTLIMPCLOCK driven on the GIOB[0] pin is the compare clock for the clock detect
PFD circuit and the source to limp clock on a clock fail.
25 RANGEDETCTRL Range detection control. This bit's functionality is dependant on the state of the
RANGEDETENSSEL bit (Bit 24) of the CLKTEST register.
0 The clock monitor range detection circuitry (RANGEDETECTENABLE) is disabled.
1 The clock monitor range detection circuitry (RANGEDETECTENABLE) is enabled.
24 RANGEDETENASSEL Selects range detection enable. This bit resets asynchronously on power on reset.
0 The range detect enable is generated by the hardware in the clock monitor wrapper.
1 The range detect enable is controlled by the RANGEDETCTRL bit (Bit 25) of the
CLKTEST register.
23-20 Reserved 0 Reads return 0. Writes have no effect.
19-16 CLK_TEST_EN Clock test enable. This bit enables the clock going to the ECLK pin.
Note: The ECLK pin must also be placed into Functional mode by setting the
ECPCLKFUN bit to 1 in the SYSPC1 register.
5h Clock going to ECLK pin is enabled.
Others Clock going to ECLK pin is disabled.
15-12 Reserved 0 Reads return 0. Writes have no effect.