Operating Modes
1120
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.2.1 Pin Configurations
The SPI supports data connections as shown in
NOTE:
1.
When the SPICS signals are disabled, the chip select field in the transmit data is not
used.
2.
When the SPIENA signal is disabled, the SPIENA pin is ignored in master mode, and
not driven as part of the SPI transaction in slave mode.
Table 24-1. Pin Configurations
Pin
Master Mode
Slave Mode
SPICLK
Drives the clock to external devices
Receives the clock from the external master
SPISOMI
Receives data from the external slave
Sends data to the external master
SPISIMO
Transmits data to the external slave
Receives data from the external master
SPIENA
SPIENA disabled:
GIO
SPIENA enabled:
Receives ENA signal from
the external slave
SPIENA disabled:
GIO
SPIENA enabled:
Drives ENA signal from the
external master
SPICS
SPICS disabled:
GIO
SPICS enabled:
Selects one or more slave
devices
SPICS disabled:
GIO
SPICS enabled:
Receives the CS signal
from the external master
24.2.2 Data Handling
shows the SPI transaction hardware. TXBUF and RXBUF are internal buffers that are
intended to improve the overall throughput of data transfer. TXBUF is a transmit buffer, while RXBUF is a
receive buffer.
24.2.2.1 Data Sequencing when SPIDAT0 or SPIDAT1 is Written
•
If both the TX shift register and TXBUF are empty, then the data is directly copied to the TX shift
register. For devices with DMA, if DMA is enabled, a transmit DMA request (TX_DMA_REQ) is
generated to cause the next word to be fetched. If transmit interrupts are enabled, a transmitter-empty
interrupt is generated.
•
If the TX shift register is already full or is in the process of shifting and if TXBUF is expty then the data
written to SPIDAT0 / SPIDAT1 is copied to TXBUF and TXFULL flag is set to 1 at the same time.
•
When a shift operation is complete, data from the TXBUF (if it is full) is copied into TX shift register
and the TXFULL flag is cleared to 0 to indicate that next data can be fetched. A transmit DMA request
(if enabled) or a transmitter-empty interrupt (if enabled) is generated at the same time.
24.2.2.2
Data Sequencing when All Bits Shifted into RXSHIFT Register
•
If both SPIBUF and RXBUF are empty, the received data in RX shift register is directly copied into
SPIBUF and the receive DMA request (if enabled) is generated and the receive-interrupt (if enabled) is
generated. The RXEMPTY flag in SPIBUF is cleared at the same time.
•
If SPIBUF is already full at the end of receive completion, the RX shift register contents is copied to
RXBUF. A receive DMA request is generated, if enabled. The receive complete interrupt line remains
high.
•
If SPIBUF is read by the CPU or DMA and if RXBUF is full, then the contents of RXBUF are copied to
SPIBUF as soon as SPIBUF is read. RXEMPTY flag remains cleared, indicating that SPIBUF is still
full.
•
If both SPIBUF and RXBUF are full, then RXBUF will be overwritten and the RXOVR interrupt flag is
set and an interrupt is generated, if enabled.
