Control Registers
296
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG)
Figure 5-41. EEPROM Emulation Configuration Register (EEPROM_CONFIG) [offset = 2B8h]
31
20
19
16
Reserved
EWAIT
R-0
R/WP-1h
15
9
8
7
0
Reserved
AUTOSUSP_EN
AUTOSTART_GRACE
R-0
R/WP-0
R/WP-2h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -
n
= value after reset
Table 5-46. EPROM Emulation Configuration Register (EEPROM_CONFIG) Field Descriptions
Bit
Field
Value
Description
31-20
Reserved
0
Reads return 0. Writes have no effect.
19-16
EWAIT
EEPROM Wait State Counter
This register will replace the RWAIT count in the EEPROM register. The same formulas that
apply to RWAIT will apply to EWAIT in the EEPROM bank.
15-9
Reserved
0
Reads return 0. Writes have no effect.
8
AUTOSUSP_EN
Auto Suspend Enable
0
Auto Suspend is disabled.
1
Auto Suspend is enabled.
The auto-suspend will begin when the CPU or Bus 2 attempts to access a bank with an
active and suspendable FSM operation. If this happens the FSM will automatically be
issued a suspend command and exit from the FSM. It will then do the access. After the
access, the FMC will wait for a time determined by the Autostart_grace field before issuing
the FSM resume command.
7-0
AUTOSTART_GRACE
Auto-suspend Startup Grace Period
1
The value in this register determines how many cycles the FMC will wait after the last CPU
or Bus 2 access before issuing the FSM resume command.
0
The FMC will wait 16 HCLK periods for each count in the AUTOSTART_GRACE field. A
value of 2 will wait for 32 periods after the last access. Each access will reset the counter to
the AUTOSTART_GRACE value × 16.
