Clocks
118
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
Table 2-11. Typical Low-Power Modes
Mode
Name
Active Clock
Source(s)
Active
Clock
Domain(s)
Wake Up Options
Suggested
Wake Up
Clock
Source(s)
Wake Up Time (wake up detected -to- CPU
code execution start)
Doze
Main oscillator
RTICLK
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
Main oscillator
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
Snooze
LF LPO
RTICLK
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
Sleep
None
None
GIO interrupt,
CAN message,
SCI message
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
2.4.3.1
Typical Software Sequence to Enter a Low-Power Mode
1. Program the flash banks and flash pump fall-back modes to be “sleep”.
The flash pump transitions from active to sleep mode only after all the flash banks have switched from
active to sleep mode. The flash banks start switching from active to sleep mode only after the banks
are not accessed for at least a duration defined by the Active Grace Period (AGP) parameter
configured for the banks. See
for more details.
2. Disable the clock sources that are not required to be kept active.
A clock source does not get disabled until all clock domains using that clock source are disabled first,
or are configured to use an alternate clock source.
3. Disable the clock domains that are not required to be kept active.
A clock domain does not get disabled until all modules using that clock domain “give their permission”
for that clock domain to be turned off.
4. Idle the Cortex-R4F core.
The ARM Cortex-R4F CPU has internal power management logic, and requires a dedicated instruction
to be used in order to enter a low power mode. This is the Wait For Interrupt (WFI) instruction.
When a WFI instruction is executed, the Cortex-R4F core flushes its pipeline, flushes all write buffers,
and completes all pending bus transactions. At this time the core indicates to the system that the clock
to the core can be stopped. This indication is used by the Global Clock Module (GCM) to turn off the
CPU clock domain (GCLK) if the CDDIS register bit 0 is set.
2.4.3.2
Special Considerations for Entry to Low Power Modes
Some bus master modules – High-End Timer Transfer Units (HTUx), Data Modification Module (DMM),
and Parameter Overlay Module (POM), can have ongoing transactions when the application wants to
enter a low power mode to turn off the clocks to those modules. This is not recommended as it could
leave the device in an unpredictable state. Refer to the individual module chapters for more information
about the sequence to be followed to safely enter a low-power mode.
